Recent digital radio communications systems employ the multi-level modulation scheme such as QPSK (Quadrature Phase Shift Keying), 8PSK, and 16QAM (Quadrature Amplitude Modulation) in order to enable high-speed transmission while effectively using limited radio frequency bands. That is, QPSK is capable of transmitting two bits by a single symbol; 8PSK is capable of transmitting three bits by a single symbol; 16QAM is capable of transmitting four bits by a single symbol. In this manner, by means of increasing the number of such multi-levels, the amount of information transmitted by a single symbol is increased, high-speed transmission being thereby realized.
Such multi-level modulation schemes arranges symbols in such a manner that distances among symbols (signal points) are equal with respect to rectangular coordinates of a real axis (I axis) and an imaginary axis (Q axis), that is, distances among symbols (signal points) are equal on a complex plane (IQ plane), in terms of lowering a symbol evaluation error (code error rate) on the receiver end as much as possible. For example, as to 16QAM, the following types are well known: a grid-like arrangement of 16 symbols at equal intervals in a grid-like arrangement (hereinafter will be called “grid-like 16QAM”) as shown in FIG. 36; a concentric type arrangement in which four symbols are arranged on the inner circle, of the double circles on a complex plane, and 12 symbols are arranged on the outer circle at the same intervals [hereinafter will be called “(4, 12) circular 16QAM”] as shown in FIG. 37; and another concentric type arrangement in which eight symbols are arranged at the same intervals on the respective same circles, the double concentric circles, on a complex plane [hereinafter will be called (8, 8) star 16QAM”] as shown in FIG. 38. Further, 8QPSK arranges eight symbols at the same intervals on a circle on a complex plane as shown in FIG. 39.
In this instance, in the symbol arrangement shown in FIG. 36, a distance ratio between a symbol close to the I axis and the Q axis to a symbol apart from those axes are given as 1:3; a radius ratio of the inner circle to the outer circle shown in FIG. 37 and FIG. 38 is given as 1:r. Such ratios should by no means be limited to these. Further, as to (4, 12) circular 16QAM shown in FIG. 37 and (8, 8) star 16QAM shown in FIG. 38, researches thereof have been proceeded from therebefore, and descriptions of such researches are made in the following non-patent documents 1 through 4.
[A] Bit Allocation (Mapping) Method to Symbols in the Multi-Level Modulation Scheme:
Here, a description will be made of a bit allocation (mapping) method in the above described grid-like 16QAM, (4, 12) circular 16QAM, (8, 8) star 16QAM, and 8PSK, with reference to FIG. 43 through FIG. 47. In this instance, in FIG. 43 through FIG. 46, a white dot indicates a bit (code) of “0”; a black dot indicates a bit of “1”.
(A1) Grid-Like 16QAM:
In a case of grid-like 16QAM, bit allocation as shown in FIG. 43, for example, is performed.
That is, as to the first bit, a bit of “1” is allocated to the first bit of each of the eight symbols arranged in the area of the left side of the Q axis [the negative area of the I axis (real axis)] on the paper, by means of quadrant decision with respect to the Q axis (imaginary axis) on the IQ plane, and a bit of “0” is allocated to the first bit of each of the eight symbols arranged on the right side (the positive area of the I axis) on the paper as shown in (1) of FIG. 43. As to the second bit, a bit of “0” is allocated to the second bit of each of the eight symbols of the upper side area of the I axis (the positive area of the Q axis) on the paper, and a bit of “1” is allocated to the second bit of each of the eight symbols of the lower side area of the I axis (the negative area of the Q axis) on the paper by means of quadrant decision with respect to the I axis as shown in (2) of FIG. 43.
Further, as to the third bit, a bit of “0” is allocated to the third bit of each of the eight symbols close to the Q axis and a bit of “1” is allocated to the third bit of each of the eight symbols apart from the Q axis, by means of distance decision from the Q axis as shown in (3) of FIG. 43. As to the fourth bit, a bit of “0” is allocated to the fourth bit of each of the eight symbols close from the I axis and a bit of “1” is allocated to the third bit of each of the eight symbols apart from the I axis, by means of distance decision from the I axis as shown in (4) of FIG. 43.
To map bits to symbols with such a method brings about a bit series allocated to each symbol as shown FIG. 47, for example, so that the bit series of adjacent symbols differ from each other only by one bit. This makes it possible to suppress a probable error down to one bit, even if the receiver end erroneously receives the adjacent symbol due to noise. In this instance, such a mapping method in which adjacent symbols differ from each other by only one bit is called “gray-mapping”.
(A2) (4, 12) Circular 16QAM:
In a case of circular 16QAM, bit allocation as shown in FIG. 44, for example, is performed.
That is, as to the first bit, a bit of “1” is allocated to the first bit of each of the eight symbols arranged on each of the circles in the area of the left side of the Q axis (the negative area of the I axis) on the paper, by means of quadrant decision with respect to the Q axis on an IQ plane, and a bit of “0” is allocated to the first bit of each of the eight symbols arranged on each of the circles of the right side area of the Q axis (the positive area of the I axis) on the paper as shown in (1) of FIG. 44. As to the second bit, a bit of “0” is allocated to the second bit of each of the eight symbols on each of the circles in the upper area of the I axis (the positive area of the Q axis) on the paper, and a bit of “1” is allocate to the second bit of each of the eight symbols on each of the circles in the lower area of the I axis (the negative area of the Q axis) on the paper, by means of quadrant decision with respect to the I axis as shown in (2) of FIG. 44.
Further, as to the third bit, a bit of “0” is allocated to the third bit of each of the eight symbols on the circle close to the Q axis, and a bit of “1” is allocated to the third bit of each of the eight symbols on the circle apart from the Q axis, by means of distance decision from the Q axis as shown in (3) of FIG. 44. As to the fourth bit, a bit of “0” is allocated to the fourth bit of each of the eight bits on the circle close from the I axis and a bit of “1” is allocated to the fourth bit of each of the eight symbols on the circle apart from the I axis, by means of distance decision from the I axis as shown in (4) of FIG. 44.
That is, in the above described grid-like 16QAM and (4, 2) circular 16QAM, bit allocation is performed to the first bits and to the second bits by means of quadrature decision with respect to the I axis and the Q axis, and bit allocation to the third bit and the fourth bit is performed by means of distance evaluation with respect to the I axis and the Q axis. The first bit and the second bit, and the third bit and the fourth bit, each have the same likelihood (quality), but the likelihood of the first bit and the second bit differs from the likelihood of the third bit and the fourth bit (the likelihood is lower than that of the first bit and the second bit).
(A3) (8, 8) Star 16QAM:
In a case of (8, 8) star 16QAM, bit allocation as shown in FIG. 45, for example, is performed.
That is, as to the first bit, a bit of “1” is allocated to the first bit of each of the eight symbols arranged on each of the circles in the area of the left side of the Q axis (the negative area of the I axis) on the paper, by means of quadrant decision with respect to the Q axis on the IQ plane, and a bit of “0” is allocated to the first bit of each of the eight symbols arranged on each of the circles of the right side area of the Q axis (the positive area of the I axis) on the paper by means of quadrant decision with respect to the I axis as shown in (1) of FIG. 45. As to the second bit, a bit of “0” is allocated to the second bit of each of the eight symbols on each of the circles in the upper area of the I axis (the positive area of the Q axis) on the paper, by means of quadrant decision with respect to the I axis as shown in (2) of FIG. 45, and a bit of “1” is allocate to the second bit of each of the eight symbols on each of the circles in the lower area of the I axis (the negative area of the Q axis) on the paper, by means of quadrant decision with respect to the I axis as shown in (2) of FIG. 45.
Further, as to the third bit, a bit of “0” is allocated to the third bit of each of the eight symbols on each of the circles arranged in the first quadrant and the third quadrant, and a bit of “1” is allocated to the third bit of each of the eight symbols on each of the circles arranged in the second quadrant and the fourth quadrant, with the evaluation reference the same as that of the third bit in a case of 8PSK, which will be described later, that is, by means of quadrant decision of a diagonal angle obtained by rotating (for example, right-handed rotation) the I axis and the Q axis 45 degrees as shown in (3) of FIG. 45. As to the fourth bit, a bit of “0” is allocated to the fourth bit of each of the eight symbols on the inner circle close to the origin point, and bit “1” is allocated to the fourth bit of each of the eight symbols on the outer circle apart from the origin point, by means of evaluation of a distance from the origin point, as shown in (4) of FIG. 45.
Accordingly, in a case of (8, 8) star 16QAM, the likelihood of the first bit is the same as the likelihood of the second bit, and the likelihood of the first bit and the second bit differs from the likelihood of the third bit and the fourth bit (lower than that of the first bit and the second bit). In addition, the likelihood of the third bit differs from that of the fourth bit. That is, (8, 8) likelihood has a three-stage likelihood.
(A4) 8PSK:
In a case of 8PSK (a single symbol is transmitted using three bits), bit allocation as shown in FIG. 46, for example, is performed.
That is, as to the first bit, a bit of “1” is allocated to the first bit of each of the eight symbols arranged on the circle in the area of the left side of the Q axis (the negative area of the I axis) on the paper, by means of quadrant decision with respect to the Q axis on the IQ plane, and a bit of “0” is allocated to the first bit of each of the eight symbols arranged on the circle of the area of the right side of the Q axis (the positive area of the I axis) on the paper as shown in (1) of FIG. 46. As to the second bit, a bit of “0” is allocated to the second bit of each of the eight symbols on the circle in the upper area of the I axis (the positive area of the Q axis) on the paper, and bit “1” is allocate to the second bit of each of the eight symbols on the circle in the lower area of the I axis (the negative area of the Q axis) on the paper, by means of quadrant decision with respect to the I axis as shown in (2) of FIG. 46.
Further, as to the third bit, a bit of “0” is allocated to the third bit of each of the eight symbols on the circle arranged in the first quadrant and the third quadrant, and a bit of “1” is allocated to the third bit of each of the eight symbols on the circle in the second quadrant and the fourth quadrant, as shown in (3) of FIG. 46, by means of quadrant decision of a diagonal angle obtained by rotating (for example, right-handed rotation) the I axis and the Q axis 45 degrees as shown in (3) of FIG. 46.
[B] System Using Turbo Code and Bit Correction Method:
As described above, in the multi-level modulation scheme, a difference of likelihood (quality) corresponding to a difference of a symbol evaluation reference in a single symbol is generated among the bits, that is, bits vulnerable to an error and bits resistant to an error are generated (generally speaking, in comparison with the first bit and the second bit allocated by means of quadrant decision with respect to the I axis and the Q axis, the third bit and the fourth bit are vulnerable to an error). Hence, as described in the following patent document 1, mapping performed without paying consideration to the quality of each bit can deteriorate the performance of decoding result on the receiver end, depending on the coding scheme.
For example, as shown in FIG. 40, a turbo coder transmits an information series [systematic bits (systematic codes)] S which is not coded and also a coded bit series [parity bits (parity codes)], such as a bit series (parity bits P1) coded by an element coder 101 and a bit series (parity bits P2) obtained by coding an information series interleaved by an interleaver 103 by an element coder 102. As described in the following patent document 1, mapping of these systematic bits and parity bits without paying consideration to the quality of each of the bits in a single symbol results in deterioration of the quality of the systematic bits in spite of the fact that the quality of systematic bits exhibits a larger effect (significance is high) to the performance of the decoding result than the quality of parity bits, so that the performance of the decoding result is deteriorated.
That is, on the receiver end (turbo decoder), as shown in FIG. 41, for example, the element decoder 201 performs decoding (soft decision) using systematic bits S and one kind of parity bits P1. After the interleaver 204 interleaves the obtained result, another element decoder 202 performs decoding thereof using systematic bits S and the other kind of parity bits P2. The deinterleaver 205 deinterleaves the decoding result, and then feedbacks the obtained result to the element decoder 201. This process is repeated a predetermined number of times, thereby performing decoding processing of turbo codes. Then, in order to finally obtain a decoded series as a result of deinterleaving the decoded result obtained by the element decoder 202 by use of the deinterleaver 206, the systematic bits S are used by the two element decoders 201 and 202, so that the effect of systematic bits S on the performance of the decoding result is greater than the effect of the quality of parity bits. In this instance, a system employing turbo coding is also described in the following patent document 2.
Thus, in systems using turbo coding, it is normally preferable that processing called bit correction be performed for improving decoding characteristic. It makes possible for systematic bits S, whose significance is higher than that of parity bits P, to be mapped to bits whose quality is high in a symbol [For example, see Chapter 4.5.4.4 (HARQ bit correction) of the following non-patent document 5]. That is, in 16QAM, of the above mentioned various types of mapping methods, as shown in FIG. 42, for example, the first bit and the second bit are superior in quality to the third bit and the fourth bit because the first and the second bit are quadrant decision in a symbol. Thus, systematic bits S and parity bits P are sequentially allocated in the vertical direction (beginning from the highest order bit toward the lowest order bit) of the paper sheet of FIG. 42, beginning from the left end row of the paper sheet as indicated by the dotted arrow so that systematic bits are allocated to the first and the second bits with high priority. In this instance, this FIG. 42 illustrates an example in which turbo coding is performed at a coding ratio=1/3. Systematic bits S are shown as S1 through S12; one kind of parity bits (obtained by the element coder 101; for example) are showed as P1-1 through P1-12; another kind of parity bits (obtained by the element coder 102) are showed as P2-1 through P2-12 (the same goes for the description hereinafter).
Patent Document 1: Japanese Patent Application Laid-open No. 2002-171298;
Patent Document 2: Japanese Patent Application Laid-open No. 2003-78419;
Non-patent Document 1: Oshita and Kondo, “Optimal Signal Point Arrangement in the 16-level Amplitude Phase Modulation Scheme”, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, August, 1989;
Non-patent Document 2: Machida, Handa, and Oshita, “(4, 12)-Type Concentric Circle Signal Arrangement and Reception Characteristic thereof in the 16-ary Amplitude Phase Modulation Scheme”, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, October, 1997;
Non-patent Document 3: F. Adachi, M. Sawahashi, “Performance Analysis of Various 16 Level Modulation Schemes under Rayleigh Fading”
Non-patent Document 4: Suzuki and Mizuno, “Multi-symbol Delay Wave Detection Scheme for Differential Motion Coding Amplitude Modulation Signals and Application thereof to 16DAPSK”, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, December, 1994; and
Non-patent Document 5: 3GPP TS 25.212 V5.2.0 (2002-09)